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EDI88512CA
512Kx8 Monolithic SRAM, SMD 5962-95600
FEATURES
Access Times of 15, 17, 20, 25, 35, 45, 55ns Data Retention Function (LPA version) TTL Compatible Inputs and Outputs Fully Static, No Clocks Organized as 512Kx8 Commercial, Industrial and Military Temperature Ranges 32 lead JEDEC Approved Evolutionary Pinout * Ceramic Sidebrazed 600 mil DIP (Package 9) * Ceramic Sidebrazed 400 mil DIP (Package 326) * Ceramic 32 pin Flatpack (Package 344) * Ceramic Thin Flatpack (Package 321) * Ceramic SOJ (Package 140) 36 lead JEDEC Approved Revolutionary Pinout * Ceramic Flatpack (Package 316) * Ceramic SOJ (Package 327) * Ceramic LCC (Package 502) Single +5V (10%) Supply Operation The EDI88512CA is a 4 megabit Monolithic CMOS Static RAM. The 32 pin DIP pinout adheres to the JEDEC evolutionary standard for the four megabit device. All 32 pin packages are pin for pin upgrades for the single chip enable 128K x 8, the EDI88128CS. Pins 1 and 30 become the higher order addresses. The 36 pin revolutionary pinout also adheres to the JEDEC standard for the four megabit device. The center pin power and ground pins help to reduce noise in high performance systems. The 36 pin pinout also allows the user an upgrade path to the future 2Mx8. A Low Power version with Data Retention (EDI88512LPA) is also available for battery backed applications. Military product is available compliant to Appendix A of MIL-PRF-38535.
FIG. 1
PIN CONFIGURATION
36 PIN TOP VIEW
A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
PIN DESCRIPTION 32 PIN TOP VIEW
32 VCC 31 A15 30 A17 29 WE 28 A13 27 A8 26 A9 25 A11 24 OE 23 A10 22 CS 21 I/O7 20 I/O6 19 I/O5 18 I/O4 17 I/O3
A
-18
I/O0-7 Data Inputs/Outputs A0-18 WE CS OE VCC VSS NC Address Inputs Write Enables Chip Selects Output Enable Power (+5V 10%) Ground Not Connected
BLOCK DIAGRAM
Memory Array
Address Buffer
Address Decoder
I/O Circuits
I/O
-7
WE CS OE
Aug. 2002 Rev. 9
1
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EDI88512CA
ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on any pin relative to Vss Operating Temperature TA (Ambient) Commercial Industrial Military Storage Temperature, Plastic Power Dissipation Output Current Junction Temperature, TJ -0.5 to 7.0 0 to +70 -40 to +85 -55 to +125 -65 to +150 1.5 20 175 Unit V C C C C W mA C OE X H L X CS H L L L WE X H H L
TRUTH TABLE
Mode Output Standby High Z Output Deselect High Z Read Data Out Write Data In Power Icc2, Icc3 Icc1 Icc1 Icc1
RECOMMENDED OPERATING CONDITIONS
Parameter Symbol Supply Voltage VCC Supply Voltage VSS Input High Voltage VIH Input Low Voltage VIL Min 4.5 0 2.2 -0.3 Typ 5.0 0 -- -- Max 5.5 0 3.0 +0.8 Unit V V V V
NOTE: Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
CAPACITANCE (TA = +25C)
Parameter Symbol Condition Max Unit Address Lines CI VIN = Vcc or Vss, f = 1.0MHz 12 pF Data Lines CO VOUT = Vcc or Vss, f = 1.0MHz 14 pF These parameters are sampled, not 100% tested.
DC CHARACTERISTICS (VCC = 5V, TA = -55C TO +125C)
Parameter Input Leakage Current Output Leakage Current Operating Power Supply Current Standby (TTL) Power Supply Current Full Standby Power Supply Current Output Low Voltage Output High Voltage Symbol ILI ILO ICC1 ICC2 ICC3 VOL VOH Conditions VIN = 0V to VCC VI/O = 0V to VCC WE, CS = VIL, II/O = 0mA, Min Cycle CS VIH, VIN VIL, VIN VIH CS VCC -0.2V VIN Vcc -0.2V or VIN 0.2V IOL = 8.0mA IOH = -4.0mA Min -10 -10 -- -- -- -- -- -- 2.4 Max 10 10 250 225 60 25 20 0.4 -- Units A A mA mA mA mA mA V V
(17ns) (20 -55ns) CA LPA
NOTE: DC test conditions: VIL = 0.3V, VIH = Vcc -0.3V
AC TEST CONDITIONS
Figure 1
Vcc
Figure 2
Vcc
Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels Output Load
480
VSS to 3.0V 5ns 1.5V Figure 1
480
NOTE: For tEHQZ, tGHQZ and tWLQZ, CL = 5pF Figure 2)
Q
255 30pF
Q
255 5pF
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2
EDI88512CA
AC CHARACTERISTICS - READ CYCLE (VCC = 5.0V, VSS = 0V, TA = -55C TO +125C)
Parameter Read Cycle Time Address Access Time Chip Enable Access Time Chip Enable to Output in Low Z (1) Chip Disable to Output in High Z (1) Output Hold from Address Change Output Enable to Output Valid Output Enable to Output in Low Z (1) Output Disable to Output in High Z(1) Symbol JEDEC Alt. tAVAV tRC tAVQV tAA tELQV tACS tELQX tCLZ tEHQZ tCHZ tAVQX tOH tGLQV tOE tGLQX tOLZ tGHQZ tOHZ 15ns Min Max 15 15 15 2 0 7 0 8 0 0 7 17ns Min Max 17 17 17 3 0 7 0 8 0 0 7 20ns Min Max 20 20 20 3 0 8 0 10 0 0 8 25ns 35ns 45ns 55ns Min Max Min Max Min Max Min Max Units 25 35 45 55 ns 25 35 45 55 ns 25 35 45 55 ns 3 3 3 3 ns 0 10 0 15 0 20 0 20 ns 0 0 0 0 ns 12 15 25 30 ns 0 0 0 0 ns 0 10 0 15 0 20 0 20 ns
1. This parameter is guaranteed by design but not tested.
AC CHARACTERISTICS - WRITE CYCLE (VCC = 5.0V, VSS = 0V, TA = -55C TO +125C)
Parameter Write Cycle Time Chip Enable to End of Write Address Setup Time Address Valid to End of Write Write Pulse Width Write Recovery Time Data Hold Time Write to Output in High Z (1) Data to Write Time Output Active from End of Write (1) Symbol JEDEC Alt. tAVAV tW C tELWH tC W tELEH tC W tAVWL tAS tAVEL tAS tAVWH tAW tAVEH tAW tWLWH tW P tWLEH tW P tWHAX tW R tEHAX tW R tWHDX tDH tEHDX tDH tWLQZ tWHZ tDVWH tD W tDVEH tD W tWHQX tWLZ 15ns 17ns Min Max Min Max 15 17 13 14 13 14 0 0 0 0 13 14 13 14 13 14 13 14 0 0 0 0 0 0 0 0 0 8 0 8 8 8 8 8 0 0 20ns 25ns 35ns 45ns Min Max Min Max Min Max Min Max 20 25 35 45 15 17 25 30 15 17 25 30 0 0 0 0 0 0 0 0 15 17 25 30 15 17 25 30 15 17 25 30 15 17 25 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 10 0 25 0 30 10 12 20 25 10 12 20 25 0 0 0 0 55ns Min Max Units 55 ns 50 ns 50 ns 0 ns 0 ns 50 ns 50 ns 45 ns 45 ns 0 ns 0 ns 0 ns 0 ns 0 30 ns 40 ns 30 ns 0 ns
1. This parameter is guaranteed by design but not tested.
3
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EDI88512CA
FIG. 2 TIMING WAVEFORM - READ CYCLE
tAVAV
ADDRESS
tAVQV
tAVAV
ADDRESS
ADDRESS 1 ADDRESS 2
CS
tELQV tELQX
OE
tEHQZ
tAVQV
DATA I/O
tAVQX
DATA 1 DATA 2
tGLQV tGLQX
DATA OUT
tGHQZ
READ CYCLE 1 (WE HIGH; OE, CS LOW)
READ CYCLE 2 (WE HIGH)
FIG. 3 WRITE CYCLE - WE CONTROLLED
tAVAV
ADDRESS
tAVWH tELWH
CS
tWHAX
tAVWL
WE
tWLWH tDVWH tWHDX
DATA IN
DATA VALID
tWLQZ
DATA OUT
HIGH Z
tWHQX
WRITE CYCLE 1, WE CONTROLLED
FIG. 4 WRITE CYCLE - CS CONTROLLED
tAVAV
ADDRESS
tAVEH tELEH
CS
WS32K32-XHX
tEHAX tWLEH tDVEH tEHDX
tAVEL
WE
DATA IN DATA OUT
HIGH Z
DATA VALID
WRITE CYCLE 2, CS CONTROLLED
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EDI88512CA
DATA RETENTION CHARACTERISTICS (EDI88512LPA ONLY) (TA = -55C TO +125C)
Characteristic Low Power Version only Data Retention Voltage Data Retention Quiescent Current Chip Disable to Data Retention Time Operation Recovery Time Sym VDD ICCDR TCDR TR Conditions VDD = 2.0V CS VDD -0.2V VIN VDD -0.2V or VIN 0.2V Min 2 - 0 TAVAV Typ - - - - Max - 2 - - Units V mA ns ns
FIG. 5 DATA RETENTION - CS CONTROLLED
DATA RETENTION MODE VCC tCDR CS CS = VDD -0.2V 4.5V VDD
WS32K32-XHX
4.5V tR
DATA RETENTION, CS CONTROLLED
5
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EDI88512CA
PACKAGE 9: 32 LEAD SIDEBRAZED CERAMIC DIP, SMD 5962-95600XXMXA
1.616 1.584
Pin 1 Indicator 0.200 0.125 0.061 0.017 0.020 0.016 15 x 0.100 = 1.500
0.060 0.040 0.155 0.115
0.620 0.600
0.100 TYP
0.600 NOM
ALL DIMENSIONS ARE IN INCHES
PACKAGE 326: 32 LEAD SIDEBRAZED CERAMIC DIP
1.616 1.584
Pin 1 Indicator 0.200 0.125 0.061 0.017 0.020 0.016 15 x 0.100 = 1.500
ALL DIMENSIONS ARE IN INCHES
1
0.420 0.400
1
0.100 TYP
0.155 0.115
0.400 NOM
PACKAGE 140: 32 LEAD CERAMIC SOJ, SMD 5962-95600XXMUA
0.010 0.006 0.019 0.015
0.840 0.820
0.444 0.430
0.379 0.155 0.106
0.050 TYP
ALL DIMENSIONS ARE IN INCHES
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EDI88512CA
PACKAGE 316: 36 PIN CERAMIC FLATPACK, SMD 5962-95600XXMTA
0.920 - 0.010 0.007 0.003 0.370 0.250 1.00 REF 0.395 0.385
0.515 0.505
Pin 1
0.040 0.030 0.019 0.015 0.125 0.100
0.045 0.020
0.050 TYP
ALL DIMENSIONS ARE IN INCHES
PACKAGE 321: 32 PIN THINPACKTM FLATPACK, SMD 5962-95600XXMYA
0.838 MAX
0.567 0.427 0.559 0.429
0.050 TYP
0.008 0.005 0.016 0.008
0.020 0.030
0.118 MAX.
ALL DIMENSIONS ARE IN INCHES
PACKAGE 344: 32 PIN CERAMIC FLATPACK, SMD 5962-95600XXM9A
ALL DIMENSIONS ARE IN INCHES
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EDI88512CA
PACKAGE 327: 36 LEAD CERAMIC SOJ, SMD 5962-95600XXMMA
0.010 0.006 0.019 0.015
0.920 0.940
0.444 0.434 0.155 0.106
0.050 TYP 0.379
ALL DIMENSIONS ARE IN INCHES
PACKAGE 502: 36 LEAD CERAMIC LCC, SMD 5962-95600XXMNA (Pending)
0.100 0.080 0.135 0.115
36 1
0.100 TYP 0.009 TYP 0.028 0.022
0.930 0.910
0.860 0.840
0.050 BSC
0.460 0.445
0.066 0.054
ALL DIMENSIONS ARE IN INCHES
White Electronic Designs Corporation * Phoenix AZ * (602) 437-1520
8
EDI88512CA
ORDERING INFORMATION
EDI 8 8 512 CA X X X
WHITE ELECTRONIC DESIGNS SRAM ORGANIZATION, 512Kx8 TECHNOLOGY: CA = CMOS Standard Power LPA = Low Power ACCESS TIME (ns) PACKAGE TYPE: C = 32 lead Sidebrazed DIP, 600 mil (Package 9) K = 36 lead Ceramic LCC (Package 502) N = 32 lead Ceramic SOJ (Package 140) T = 32 lead Sidebrazed DIP, 400 mil (Package 326) B32 = 32 pin Ceramic ThinpackTM Flatpack (Package 321) F32 = 32 pin Ceramic Flatpack (Package 344) F36 = 36 pin Ceramic Flatpack (Package 316) N36 = 36 lead Ceramic SOJ (Package 327) DEVICE GRADE: B = MIL-STD-883 Compliant M = Military Screened I = Industrial C = Commercial
-55C to +125C -40C to +85C 0C to +70C
9
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